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GALVANTECH, INC. ASYNCHRONOUS SRAM
FEATURES
* * * * * * * Fast access times: 8, 10, and 12ns Fast OE# access times: 5 and 6ns Single +5V +10% power supply Fully static -- no clock or timing strobes necessary All inputs and outputs are TTL-compatible Three state outputs High-performance, low-power consumption, CMOS double-poly, double-metal process
GVT7232A8 TRADITIONAL PINOUT 32K X 8 SRAM
32K x 8 SRAM
+5V SUPPLY, SINGLE CHIP ENABLE TRADITIONAL PINOUT
GENERAL DESCRIPTION
The GVT7232A8 is organized as a 32,768 x 8 SRAM using a four-transistor memory cell with a high performance, silicon gate, low-power CMOS process. Galvantech SRAMs are fabricated using double-layer polysilicon, double-layer metal technology. Static design eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers one chip enable (CE#) along with output enable (OE#) for this organization. The chip is enabled when CE# is LOW. With chip being enabled, writing to this device is accomplished when write enable (WE#) is LOW and reading is accomplished when (OE#) go LOW with (WE#) remaining HIGH. The device offers a low power standby mode when chip is not selected. This allows system designers to meet low standby power requirements.
OPTIONS
* Timing 8ns access 10ns access 12ns access Packages 28-pin SOJ (300 mil) 28-pin TSOP Power consumption Standard Low Temperature Commercial Industrial
MARKING
-8 -10 -12
*
SJ TS
*
None L
PIN ASSIGNMENT 28-Pin SOJ 28-Pin TSOP
(0C to 70C) (-40C to 85C)
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
*
None I
VCC WE# A13 A8 A9 A11 OE# A10 CE# DQ8 DQ7 DQ6 DQ5 DQ4
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051 Tel (408) 566-0688 Fax (408) 566-0699
Rev. 2/98
Galvantech, Inc. reserves the right to change products or specifications without notice.
GALVANTECH, INC.
FUNCTIONAL BLOCK DIAGRAM
GVT7232A8 TRADITIONAL PINOUT 32K X 8 SRAM
VCC VSS A0 DQ1
ROW DECODER
ADDRESS BUFFER
MEMORY ARRAY 256 ROWS X 128 X 8 COLUMNS
I/O CONTROL
DQ8
CE# WE#
OE#
A14
COLUMN DECODER
POWER DOWN
TRUTH TABLE
MODE READ WRITE OUTPUT DISABLE STANDBY CE# L L L H WE# H L H X OE# L X H X DQ Q D HIGH-Z HIGH-Z POWER ACTIVE ACTIVE ACTIVE STANDBY
PIN DESCRIPTIONS
Pin Numbers
10, 9, 8, 7, 6, 5, 4, 3, 25, 24, 21, 23, 2, 26, 1 27 20
SYMBOL
A0-A14
TYPE
Input
DESCRIPTION
Addresses Inputs: These inputs determine which cell is addressed.
WE# CE#
Input
Write Enable: This input determines if the cycle is a READ or WRITE cycle. WE# is LOW for a WRITE cycle and HIGH for a READ cycle. Chip Enable: This input is used to enable the device. When CE# is LOW, the chip is selected. When either CE# is HIGH, the chip is disabled and automatically goes into standby power mode. Output Enable: This active LOW input enables the output drivers. SRAM Data I/O: Data inputs and data outputs
Input
22 11, 12, 13, 15, 16, 17, 18, 19 28 14
OE# DQ1-DQ8 VCC VSS
Input Input/ Output
Supply Power Supply: 5V +10% Supply Ground
February 5, 1998
2
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GALVANTECH, INC.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS........-0.5V to +7.0V VIN ..........................................................-0.5V to VCC+0.5V Storage Temperature (plastic) ..........................-55oC to +125o Junction Temperature .....................................................+125o Power Dissipation ...........................................................1.2W Short Circuit Output Current .......................................50mA
GVT7232A8 TRADITIONAL PINOUT 32K X 8 SRAM
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(All Temperature Ranges; VCC = 5V +10% unless otherwise noted)
DESCRIPTION
Input High (Logic 1) voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage 0V < VIN < VCC Output(s) disabled, 0V < VOUT < VCC IOH = -4.0mA IOL = 8.0mA
CONDITIONS
SYMBOL
VIH VIl ILI ILO VOH VOL VCC
MIN
2.2 -0.5 -5 -5 2.4
MAX
VCC+1 0.8 5 5
UNITS
V V uA uA V
NOTES
1, 2 1, 2
1 1 1
0.4 4.5 5.5
V V
DESCRIPTION
Power Supply Current: Operating TTL Standby CMOS Standby
CONDITIONS
Device selected; CE# < VIL; VCC =MAX; f=fMAX; outputs open CE# >VIH; VCC = MAX; f=fMAX CE# >VCC -0.2; VCC = MAX; all other inputs < VSS +0.2 or >VCC -0.2; all inputs static; f= 0
SYM
Icc ISB1 ISB2
TYP
60 20 0.75
POWER
-8*
170 160 45 40 5 5
-10
145 135 41 36 5 5
-12
125 115 37 32 5 5
UNITS NOTES mA mA mA 3, 14 14 14
standard low standard low standard low
*NOTE: VCC = 5V + 5% for this speed grade. CAPACITANCE
DESCRIPTION
Input Capacitance Input/Output Capacitance (DQ)
CONDITIONS
TA = 25oC; f = 1 MHz VCC = 5V
SYMBOL
CI CI/O
MAX
6 8
UNITS
pF pF
NOTES
4 4
February 5, 1998
3
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GALVANTECH, INC.
AC ELECTRICAL CHARACTERISTICS
(Note 5) (All Temperature Ranges; VCC = 5V
DESCRIPTION
READ Cycle READ cycle time Address access time Chip Enable access time Output hold from address change Chip Enable to output in Low-Z Chip disable to output in High-Z Output Enable access time Output Enable to output in Low-Z Output Enable to output in High-Z Chip Enable to power-up time Chip disable to power-down time WRITE Cycle WRITE cycle time Chip Enable to end of write Address valid to end of write, with OE# HIGH Address setup time Address hold from end of write WRITE pulse width WRITE pulse width, with OE# HIGH Data setup time Data hold time Write disable to output in Low-Z Write Enable to output in High-Z
tWC tCW tAW tAS tAH tWP2 tWP1 tDS tDH tLZWE tHZWE tRC tAA tACE tOH tLZCE tHZCE tAOE tLZOE tHZOE tPU tPD
GVT7232A8 TRADITIONAL PINOUT 32K X 8 SRAM
+10%)
- 8* - 10
MIN MAX
- 12
MIN MAX UNITS NOTES
SYM
MIN
MAX
8 8 8 2 3 5 5 0 5 0 8 8 6 6 0 0 8 6 5 0 3 5
10 10 10 2 3 5 5 0 5 0 10 10 7 7 0 0 10 7 5 0 3 5
12 12 12 2 3 6 6 0 6 0 12 12 8 8 0 0 10 8 6 0 3 6
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4, 7 4, 6, 7 4, 6 4 4 4, 7 4, 6, 7
*NOTE: VCC = 5V + 5% for this speed grade.
February 5, 1998
4
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GALVANTECH, INC.
AC TEST CONDITIONS Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Output load 0V to 3.0V 1.5ns 1.5V 1.5V See Figures 1 and 2
GVT7232A8 TRADITIONAL PINOUT 32K X 8 SRAM
OUTPUT LOADS
Q Z0 = 50 50 Vt = 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT +5V 480 Q 255 5 pF 30 pF
Fig. 2 OUTPUT LOAD EQUIVALENT
NOTES
1. 2. 3. 4. 5. 6. 7. All voltages referenced to VSS (GND). Overshoot: Undershoot: VIH +7.0V for t tRC /2. VIL -2.0V for t tRC /2
8. 9.
WE# is HIGH for READ cycle. Device is continuously selected. Chip enable and output enables are held in their active state.
Icc is given with no output current. Icc increases with greater output loading and faster cycle times. This parameter is sampled. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. Output loading is specified with CL=5pF as in Fig. 2. Transition is measured +500mV from steady state voltage. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE.
10. Address valid prior to, or coincident with, latest occurring chip enable. 11. tRC = Read Cycle Time. 12. Chip Enable and Write Enable can initiate and terminate a WRITE cycle. 13. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1. 14. Typical values are measured at 5V, 25oC and 20ns cycle time.
February 5, 1998
5
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GALVANTECH, INC.
GVT7232A8 TRADITIONAL PINOUT 32K X 8 SRAM
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
VIH VIL
4.5V
t
V
DR
4.5V
tRC
CDR
CE#
READ CYCLE NO. 1(8, 9)
t
RC
ADDR
t t
VALID
AA
OH
Q
PREVIOUS DATA VALID
READ CYCLE NO. 2(7, 8, 10, 12)
tRC
DATA VALID
CE#
tAOE tLZOE
OE#
tACE tLZCE
tHZCE
tHZOE
Q
HIGH Z
DATA VALID DON'T CARE UNDEFINED 6
February 5, 1998
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GALVANTECH, INC.
GVT7232A8 TRADITIONAL PINOUT 32K X 8 SRAM
WRITE CYCLE NO. 1(7, 12, 13) (Write Enable Controlled with Output Enable OE# active LOW))
tWC
ADDR
tAW t tAH
CW
CE#
tAS
tWP2
WE#
tDS tDH
D
tHZWE
DATA VALID
tLZWE
Q
HIGH Z
WRITE CYCLE NO. 2(12, 13) (Write Enable Controlled with Output Enable OE# inactive HIGH)
tWC
ADDR
tAW t tAH
CW
CE#
tAS t
WP1
WE#
tDS tDH
D Q
DATA VALID HIGH Z DON'T CARE UNDEFINED
February 5, 1998
7
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GALVANTECH, INC.
GVT7232A8 TRADITIONAL PINOUT 32K X 8 SRAM
WRITE CYCLE NO. 3(12, 13) (Chip Enable Controlled)
t
WC
ADDR
tAW t tAH t
AS
CW
CE#
tWP1
WE#
tDS tDH
D
DATA VALID HIGH Z
Q
DON'T CARE
February 5, 1998
8
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GALVANTECH, INC.
Package Dimensions
GVT7232A8 TRADITIONAL PINOUT 32K X 8 SRAM
28-pin 300 Mil Plastic SOJ (SJ)
.730 (18.54) .697 (17.70)
.305 (7.75) .292 (7.42)
.347 (8.81) .327 (8.31)
PIN #1 INDEX
.050 (1.27) TYP
.140 (3.54) .120 (3.04)
SEATING PLANE .020 (0.51) .014 (0.36)
.095 (2.41) .080 (2.03) .275 (6.99) .260 (6.60) .025 (0.63) MIN
Note: All dimensions in inches (millimeters)
MAX MIN
or typical, min where noted.
28-pin Plastic TSOP (TS)
.536 (13.60) .520 (13.20) .011 (0.27) .006 (0.15)
.022 (0.55) TYP .319 (8.10) .311 (7.90)
.047 (1.20) MAX
.468 (11.90) .460 (11.70) .008 (0.20) .002 (0.05)
Note: All dimensions in inches (millimeters)
MAX MIN
or typical, max where noted.
February 5, 1998
9
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GALVANTECH, INC.
GVT7232A8 TRADITIONAL PINOUT 32K X 8 SRAM
Ordering Information GVT 7232A8 XX - XX X X
Galvantech Prefix Part Number Temperature (Blank = Commercial I = Industrial) Power (Blank= Standard, L= Low Power) Speed (8 = 8ns, 10= 10ns 12 = 12ns) Package (SJ= 300 mil SOJ, TS= TSOP)
February 5, 1998
10
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98

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